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Tag: soc
SoC Implementation Software accelerates optimized design delivery.
2015-03-18 13:31:08| Industrial Newsroom - All News for Today
Driven by massively parallel architecture, Innovus™ Implementation System helps SoC developers accelerate delivery of designs with optimized power, performance, and area (PPA). Physical implementation solution typically provides 10%–20% better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10 nm FinFET processes and established process nodes. Features include GigaPlace solver-based placement technology, slack-driven routing, and full-flow multi-objective technology.
Tags: software
design
delivery
implementation
Next Generation SoC Addition to Apalis Computer Module Family
2015-03-16 11:31:15| Industrial Newsroom - All News for Today
NVIDIAs presentation of their latest generation Tegra TX1 system on chip (SoC) by their CEO and co-founder Jensen Huang at CES 2015, and their live demo of the TX1 powered Shield at GDC 2015, has created a lot of excitement here at Toradex. Never before was it possible to perform such powerful multi-stream...
Tags: family
computer
addition
generation
Altera Demonstrates Its Comprehensive FPGA, SoC and Power Solutions at APEC 2015 Offering Greater Efficiencies in Electronic Design
2015-03-16 11:31:15| Industrial Newsroom - All News for Today
Solutions for Integrated Digital DC-DC Power Conversion, Envelope Tracking Voltage Modulation, and Multi-axis Motor Control SAN JOSE, Calif. and CHARLOTTE, N.C., -- APEC 2015 - Altera Corporation (NASDAQ: ALTR) is demonstrating its portfolio of FPGA and power solutions at the Applied Power Electronics Conference...
Tags: design
power
solutions
electronic
Synopsys' IC Compiler II Enables Toshiba's Tapeout of Complex 40-nm SoC, Proves out Game-Changing Capabilities
2015-03-12 11:31:11| Industrial Newsroom - All News for Today
Toshiba Standardizes on IC Compiler II for Physical Design MOUNTAIN VIEW, Calif. - Highlights: -- IC Compiler II enables Toshiba's successful tapeout of advanced 40-nm SoC -- 6X faster design turnaround time with one-third of the memory footprint -- 60 percent smaller buffer area during...
Tags: out
complex
enables
capabilities
Verification IP optimizes FPGA and SoC design reliability.
2015-03-11 13:31:08| Industrial Newsroom - All News for Today
Supporting FPGA and SoC designs based on ARM AMBA 4 architecture, plug-and-play AXI4 Verification IP was developed in SystemVerilog and is available for OVM, VMM, and UVM verification methodologies. Reusable, configurable, and pre-verified, AXI4 VIP supports functional coverage for checkers to ensure IP/RTL behavior is continuously monitored. For faster debug cycles, solution includes features such as Transaction Tracker and Bandwidth Monitor.
Tags: design
reliability
soc
verification
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