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MIPI Subsystem helps accelerate designs' market introduction.
2015-04-07 14:31:07| Industrial Newsroom - All News for Today
MIPI subsystem, consisting of Camera Serial Interface (CSI-2) and Low-Voltage Differential Signaling (LVDS) in UMC's 40 nm LP process, also includes Co-IP (Composite IP), prototype, and system loopback testing. Co-IP integrates combo PHY IP, MIPI CSI-2 RX controller, and LDVS controller and is configurable for various sensor interfaces to support transmission speeds to 1 Gbps for each of 4 data lanes. Prototype (combo PHY EVB and controller FPGA code) helps advance designs to pre-silicon stage.
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introduction
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