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Test System optimizes performance of NVMe PCIe SSDs.
2013-07-23 14:29:58| Industrial Newsroom - All News for Today
Operating over PCIe Gen 2.0 and Gen 3.0 communication protocols, NVMe Test System enables variable device throughputs up to 8 Gbps per lane through specific PCIe lane architecture. Open source, standardized, low-latency host driver and set provides flexible command queue structure featuring 64 k queues with 64 k entries each. Available on Environmental, Burn-in, and Bench-top systems, solution supports SATA TRIM command to identify old data blocks that can be reclaimed by device. This story is related to the following:Communications Testers |
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