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David Murray says ASIC must be exempt from Public Service Act so it can raise pay
2015-08-26 12:32:02| Automakers - Topix.net
The corporate cop needs more money that is independent of the government because it is busiest when governments are cutting back, financial system inquiry head David Murray says. The Australian Securities and Investments Commission should also be exempt from the Public Service Act so it can pay its people more, the former Commonwealth Bank of Australia chief said.
ASIC Designer Concepteur ASIC
2015-07-17 19:03:46| Space-careers.com Jobs RSS
MDAs Digital Department is looking for engineers with experience in the design of large ASICs. These ASICs will be at the heart of a complex digital signal processing unit that will be part of new generation communication satellites. Knowledge of VHDL or Verilog and associated design tools for the preliminary FPGA implementation is essential. Candidates must have experience in ASIC synthesis timing analysis. Responsibilities Knowledge of Synplify, Xilinx Vivado,Modelsim, Synopsys DC Ultra, Synopsys PrimeTime Knowledge of UnixLinux environment and script languages CShell, Tcl Comfortable for doing lab debugging Exposure to space radiation effects on electronic components Knowledge of AMBA AXI4, CANBus, SpaceWire, 1553 digital busses, Serdes Familiarity with automated verification techniques for test benches Exposure to Microsemi Libero Designer, System Verilog, UVM Experience with communication systems Matlab Requirements Electrical Engineering EE or equivalent Bachelors degree Ten 10 years or more of experience designing ASICs Strong interpersonal skills and an ability to work well in a team. Excellent verbal and written communication skills in French and English. Le service numrique de MDA est la recherche dingnieurs avec une exprience en conception de grands ASIC. Ces ASIC seront au cur dun grand processeur de signaux numriques complexe qui fera partie des satellites de tlcommunications de la nouvelle gnration. La connaissance de VHDL ou de Verilog et des outils de conception connexes pour limplmentation prliminaire FPGA est essentielle. Les candidats doivent avoir de lexprience en synthse ASIC et en analyse de temps. Responsabilits Connaissance de Synplify, Xilinx Vivado,Modelsim, Synopsys DC Ultra, Synopsys PrimeTime Connaissance de lenvironnement UnixLinux et des langages de script CShell, Tcl laise effectuer du dbogage de laboratoire Exposition aux effets du rayonnement spatial sur les composants lectroniques Connaissance dAMBA AXI4, CANBus, SpaceWire, 1553 digital busses, Serdes Familiarit avec les techniques de vrification automatises pour les bancs dessai Exposition Microsemi Libero Designer, System Verilog, UVM Exprience avec les systmes de communication Matlab Exigences Baccalaurat en gnie lectrique ou quivalent Dix 10 ans ou plus dexprience en conception ASIC Excellentes habilets en communications interpersonnelles et capacit de bien travailler en quipe. Excellentes aptitudes communiquer en franais et en anglais, loral et lcrit.
Tags: designer
asic
concepteur
TowerJazz And Anatrix Develop RadHard RF ASIC; Reaches Flight Qualification
2015-07-14 10:44:50| rfglobalnet Home Page
TowerJazz, the global specialty foundry leader, and Anatrix, a provider of custom analog, RF and mixed-signal IC solutions, developed a Radiation Hardened (RadHard) by Design RF front end ASIC (application specific integrated circuit) utilizing TowerJazz's 0.18-micron SiGe BiCMOS (SBC18HA) process through its U.S. Aerospace & Defense business unit in its Newport Beach, CA facility.
Tags: develop
flight
reaches
qualification
Key ASIC Deploys Synopsys' Design Compiler Graphical to Accelerate System-on-Chip Design
2015-07-09 12:31:18| Industrial Newsroom - All News for Today
Delivers Higher Frequency and Smaller Area Compared to Other Synthesis Solutions MOUNTAIN VIEW, Calif. Highlights: Key ASIC has deployed Design Compiler Graphical to accelerate the design implementation of its consumer, wireless and personal electronics ICs Comprehensive evaluation of available synthesis...
Tags: design
key
graphical
accelerate
ASIC and FPGA Engineer x2
2015-07-07 17:05:59| Space-careers.com Jobs RSS
Airbus Defence and Space is a division of Airbus Group formed by combining the business activities of Cassidian, Astrium and Airbus Military. The new division is Europes number one defence and space enterprise, the second largest space business worldwide and among the top ten global defence enterprises. It employs some 40,000 employees generating revenues of approximately 14 billion per year. Two vacancies for ASIC and FPGA Engineers have arisen within the Communication Processor Group TEOHU1 with Airbus Defence and Space based in Stevenage. The Communication Processor Group is responsible for the development of digital processors for Space telecommunication applications to a variety of customers. You will be responsible for the design and delivery of complex ASIC and FPGA designs to satisfy the projects requirements. You will be subject to UK security clearance in order to undertake related work in accordance with business needs. The successful candidates will be subject to UK National Security Clearance in order to undertake related work in accordance with business needs. Your main tasks and responsibilities will include Agree a requirement specification with Systems Design team that can be delivered and validated to meet the project schedule. Estimate the effort required to complete the design. Delivery of the design to cost, schedule and quality. Decomposing the requirement specification into an architecture design and document the chosen design whilst describing any tradeoffs performed. Detailed RTL design in VHDL for a high reliability space design. Verification of the RTL design and documenting the verification that was performed. Gate level implementation of the design including Synthesis and Static Timing Analysis. Performing a Single Event Effects analysis of the design. Production test vector generation for ASIC design. Support integration of the ASIC FPGA into the target hardware. Ensure that all ASIC and FPGA designs are developed in accordance with the company design process. Support customer design reviews. This role will involve some travels for business and as such you must be able to travel accordingly. We are looking for candidates with the following skills and experience Educated to degree level in Electrical and Electronic Engineering or related discipline. Extensive experienced in the complete design flow from requirements to design acceptance. Extensive experienced in FPGA vendor tools including Xilinx ISE and Microsemi Libero and in FPGA technologies ideally those suitable for Space. Experienced in VHDL simulation tools in particular Mentor Graphics Questa. Experienced in synthesis and STA tools ideally those from Synopsys. Experienced in ASIC production vector tools ideally those from Mentor Graphics. Experience of the Linux operating system would be beneficial. Knowledge of scripting languages including TCL and PERL. Proven track record of delivering on cost, on schedule and on quality. Good analytical skills and methodical approach to problem resolution and investigations. Good communication skills and able to thrive in a team environment. Ability to present technical data in a clear and concise manner. Understanding of digital signal processors would be beneficial. Negotiation level in English. Please apply on line for this vacancy using your eRecruiting profile with your CV attached. Airbus Group is committed to achieving workforce diversity and creating an inclusive working environment. We welcome all applications irrespective of social and cultural background, age, gender, disability, sexual orientation or religious belief. Airbus Group Recruitment Centre To apply click here