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Tag: design
Cathedral Park | 9-19-16 | 6620 N Richmond Ave | Type II Design Review - Pre-Application Conference | EA 16-238729
2016-09-20 00:58:34| PortlandOnline
PDF Document, 629kbCategory: Pre-Application Conferences
Buckman | 9-19-16 | 525 SE MLK BLVD | Type III Design Review - Pre-Application Conference | EA 16-236373
2016-09-20 00:55:26| PortlandOnline
PDF Document, 575kbCategory: Pre-Application Conferences
Goltens Green Technologies-Ship Repair, Design and Engineering Services
2016-09-16 12:07:00| Ship Technology
Goltens Green Technologies provides ship repair services in order to keep vessels in operation.
Tags: services
design
green
engineering
Sea-Tac unveils design images for North Satellite terminal upgrade
2016-09-16 01:00:00| Airport Technology
The Port of Seattle in the US has unveiled the first videos and the final design images for the modernisation of the North Satellite terminal at Seattle-Tacoma International Airport.
Tags: design
north
images
upgrade
Microelectronics Design and Validation Support Engineer
2016-09-15 16:03:37| Space-careers.com Jobs RSS
Ajilon Technology Aerospace is looking for a Microelectronics Design and Validation Support Engineer E3 for an opportunity at the European Space Agency in the Netherlands Ajilon Technology Aerospace is a specialized Engineering consultancy with more than 30 years experience providing aerospace Engineers to our key partners in The Netherlands. Ajilon is a longstanding business partner of the European Space Agency ESA, with more than 100 employees recruited from across Europe currently supporting ESAs activities. Overview Provision of VLSI ASIC FPGA technical expertise to Projects involving requirements analysis, performance and budgets analysis, writing and assessment of VLSI specifications review, evaluation and checking of industrial contractors VLSI designs. Identification of design deficiencies and problem areas and proposals for their solutions. Design, analysis, verification of VLSI systems for control and data processing applications, andor signal processing using industrial standard tools, hardware description and programming languages. Specific tasks Being the Focal Point of ESA IP Cores Service technical and administrative maintenance of our catalogue of IP Cores. This work includes verifying, improving and correcting the IP Cores source code good working knowledge of VHDL and SystemC and IC EDA tools is therefore mandatory and documentation based on users feedback, maintaining the databases and tools used for the service, interacting with customers and our legal department to solve technical, legal and administration problems. Microelectronics Laboratory Coordination conditioning and maintenance of the laboratory infrastructure, servers, CAD tools, new equipment, equipment and components inventory, security in the lab. Support in the lab to trainees and research scientists. Microelectronics website main curator regular updates to disseminate our ESA Microelectronics group RD main lines and results, and WorkshopConference announcements, etc. Internal validation of new ASIC, FPGA and IP Core designs and technologies. Maintaining test bench environments for key general use new devices such as Next Generation Microprocessors and FPGAs. Support in the lab to trainees and research scientists. Technical and administrative management of the ESA SystemC and synthesizable VHDL IP Core pool of designs. This work will involve optimisation, update and overall maintenanceand of the ESA VHDL IP Cores databases, provision of technical support to ESA IP Cores users performing analysis and finding solutions to problems in VHDL code, documentation or design methodology holding a strong collaboration with our Contracts department in arranging and solving licences and patent issues. Advertising the ESA IP service website, workshops, etc, handling IP cores requests and their distribution. The post holder will support ASIC andor FPGA technology developments for RD and or projects, supervising that good design practices and manufacturing and test methodologies are applied. In addition, independent verification through code inspection, simulation and timing analysis and validation through HW tests will have to be carried out for some ASIC and FPGAS developments. Furthermore, The Contractor shall perform the following tasks When asked to support development contracts regarding the above areas, the Contractor shall act as the activity technical responsible, maintain interfaces with the prime contractors, participate in progress meetings and reviews, as requested, and provide appropriate feedback on the achieved progress and discussions. When supporting projects, heshe shall interfaces with ESAs project teams, the prime and lower level contractors, participate in progress meetings and reviews, as requested by project work, and provide appropriate feedback on the achieved progress and discussions. To successfully perform the above mentioned tasks, the following background experience is required Applicants should have a Masters degree in Electronics Engineering or Physics, specialized in microelectronics. Applicants should have four or more years of experience in Design and test of digital ASICs andor FPGAs specifications, block design, top level integration, design for test, pre and post layout simulation and timing analysis, gates synthesis, support during layout, prototype test and in system validation, with proficiency in HDL VHDL, Verilog and SystemC and using VLSI IC Design CAD tools Synopsys, CADENCE, Mentor, Mathlab, Simulink, Xilinx, MicrosemiACTEL, Altera, Atmel. Significant experience in ASICFPGA design, HDL coding and EDA tools is essential. Preparation of ASIC or FPGA testbenchs, for functional validation and electrical characterization, using signal generators, oscilloscopes and signal analyzers. System administration in UNIX and Windows for IC Design CAD tools Synopsys, CADENCE, Mentor, Mathlab, Simulink Important additional assets would be Experience with Microprocessors e.g. LEON and HWSW codesign Experience with analog and mixedsignal ASIC design. Knowledge of the Space environment, its effects on microelectronics devices and related technology, as well as quality standards applied to space VLSI ICs. Experience with radiation tests of VLSI ASICs The candidate should have good interpersonal communication skills and high motivation to work in a multidisciplinary and international environment with confidence and autonomy. The working languages of the Agency are English and French. Agood knowledge of one of these two languages is required. Knowledge of another member state language is an asset. Experience with using third party Intellectual Property IP designs in VHDL andor SystemC is a requirement. About ESAESTEC The European Space Agency ESA has sites in several European countries. The European Space Research and Technology Centre ESTEC is the largest site and the technical heart of ESA. This nursery of European space activities is located in Noordwijk, Netherlands. At ESTEC, about 2500 engineers, technicians and scientists work handson with mission design, spacecraft and space technology. Almost all ESA projects except launchers are managed from ESTEC. In Noordwijk, people work on science missions, manned space missions, Earth observation, telecommunications and navigation satellites. ESTEC provides extensive testing facilities to verify the proper operation of spacecraft, such as the Large Space Simulator LSS, acoustic and electromagnetic testing bays, multiaxis vibration tables and the ESA Propulsion Laboratory EPL. Please send your CV to technologyaerospaceajilon.nl before 26092016
Tags: support
design
engineer
validation
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