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Agilent Technologies to Showcase Bit Error Ratio Tester at DesignCon

2013-01-24 06:00:00| Industrial Newsroom - All News for Today

New Options Enable 32-Gb/s ASIC Component and Optical Transceiver Designs SANTA CLARA, CA.- Agilent Technologies Inc. (NYSE: A) today announced it will demonstrate a 32-Gb/s bit error ratio tester with fast rise time and higher output amplitude at DesignCon (Booth 201) in Santa Clara Convention Center, Jan. 29-30. A new era of data center infrastructure enabling cloud computing, big data and analytics is driving the development of new high-speed data transfer standards such as 100-Gb ...This story is related to the following:Communication Systems and EquipmentSearch for suppliers of: Bit Error Rate (BERT) Testers |

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