Richardson, TX – Visibility into the operations and data stored on circuit boards and in semiconductors is the goal of test and debug. Unfortunately, this is often at odds with the goals of circuit board security. A new eBook published by ASSET® InterTech (<a href="http://www.asset-intertech.com">www.asset-intertech.com</a>) addresses the inherent weaknesses in the IEEE 1149.1 Boundary-Scan (JTAG) standard’s Test Access Port (TAP) found on many circuit boards and chips, and ...