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Cadence Achieves First PCI Express 2.0 and PCI Express 3.0 Compliance for TSMC 16nm FinFET Plus Process

2015-03-02 11:31:13| Industrial Newsroom - All News for Today

Multi-protocol PHY supports PCI Express 2.0, PCI Express 3.0, USB 3.0 and SGMII specifications SAN JOSE, Calif.  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its multi-protocol Serializer/Deserializer (SerDes) PHY IP for PCI Express (PCIe) 2.0 and PCIe 3.0 technology for TSMC's 16nm FinFET...

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