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Cadence Achieves PCIe 3.0 Compliance for PHY and Controller IP
2014-07-29 06:00:00| Industrial Newsroom - All News for Today
SAN JOSE, Calif. — Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced that its PHY IP and Controller IP for PCI Express® (PCIe®) 3.0 have passed certification tests from PCI-SIG®. The solutions were tested to their full potential and complied with the full speed of 8GT/s for PCIe 3.0 technology. The compliance assures designers that their system-on-chip (SoC) designs will operate as expected.<br /> <br /> "As a PCI-SIG member for more than 10 ...This story is related to the following:Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores
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Category:Industrial Goods and Services