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Clock Jitter Attenuator supports JESD204B interface standard.

2015-09-15 14:31:07| Industrial Newsroom - All News for Today

Delivering 50 fs jitter performance, 3.2 GHz Model HMC7044 supports JESD204B serial interface standard for connecting high-speed data converters and FPGAs operating in base station designs. Device generates source-synchronous and adjustable sample and frame alignment clocks in data converter system. Housed in 68-lead 10 x 10 mm LFCSP package, IC features 2 PLLs and overlapping, on-chip VCOs. It offers low phase noise of < -142 dBc/Hz at 800 kHz to 983.04 MHz output frequency.

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Category:Industrial Goods and Services

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