Home › DDR4 PHY IP targets microserver market.
 

Keywords :   


DDR4 PHY IP targets microserver market.

2014-05-28 14:31:47| Industrial Newsroom - All News for Today

Built on 16 nm FinFET process, Cadence® DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers realize maximum performance of DDR4 standard, which is specified to scale up to 3,200 Mbps. This story is related to the following:Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores

Tags: market targets phy

Category:Industrial Goods and Services

Latest from this category

All news
15.09Your MANA RepFinder Profile
13.09A League of Their Own Womens Special Interest Group Invites You to Attend a MANAchat on September 26
Industrial Goods and Services »
23.09Australia supermarkets sued over fake discount claims
23.09Tropical Depression Ten-E Public Advisory Number 1A
23.09Summary for Tropical Depression Ten-E (EP5/EP102024)
23.09Tropical Depression Ten-E Graphics
23.09Eastern North Pacific Tropical Weather Outlook
23.09Atlantic Tropical Weather Outlook
22.09Tropical Depression Ten-E Forecast Discussion Number 1
22.09Tropical Depression Ten-E Graphics
More »