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Design Kit optimizes all SoC processor cores.
2013-06-18 14:29:20| Industrial Newsroom - All News for Today
Available as add-on to DesignWare® Duet Embedded Memory and Logic Library IP, DesignWare HPC Design Kit contains suite of high-speed and high-density memory instances and standard cell libraries that enable SoC designers to optimize on-chip CPU, GPU, and DSP IP cores for maximum speed, smallest area, or lowest power. To minimize dynamic and leakage power as well as die area, kit provides area-optimized and multi-bit flip-flops and 2-port SRAM. This story is related to the following:Computer Hardware and PeripheralsSearch for suppliers of: Software Development Tools | SRAM Modules
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