Offering automated solution for testing analog/mixed-signal IP, digital logic blocks, memory, and interface IP, DesignWare® STAR Hierarchical System creates user-configurable IEEE 1500 interfaces in RTL for each IP and logic block in SoC and integrates them with top-level control module or server while maintaining standard interface at every design hierarchy level. Automatic creation of hierarchical network optimizes area and signal routing and minimizes test integration time.
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