In addition to providing foundation of design closure technologies, IC Compiler™ 2013.03 features optimizations that enable high-speed design; efficient implementation of final-stage engineering change orders (ECO); and fully color-ready, tapeout-proven support for emerging FinFET-based silicon processes. To enable high-speed clock design, clock estimation is performed during placement to drive physical- and timing-aware clock gating concurrently with clock and data optimization.
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