Tensilica® Imaging and Video Processor-Enhanced Performance (IVP-EP) core is available as configurable core and complete, pre-built subsystem. Integrating DMA transfer engine with up to 10 GBps throughput and local memory throughput of 1,024 bits per cycle, 4-way VLIW architecture delivers parallelism intermixed with code-compact instructions, with 32-way vector SIMD dataset. Imaging-specific operations accelerate 8-, 16-, and 32-bit pixel data types and video operation patterns.
This story is related to the following:Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores