Using JNEye software, designers can evaluate high-speed serial link performance in FPGAs and SoCs. Tool combines speed of statistical link simulator with accuracy of time-domain waveform-based simulator to form hybrid behavioral simulation paradigm. Device characterization models accurately account for process, voltage, and temperature variations. In addition to optimizing transmit/receive equalization coefficients for target bit error ratios, tool can assist in post-design debug and validation.
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