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On-Chip Network improves memory subsystem support and QoS.
2014-07-28 14:31:13| Industrial Newsroom - All News for Today
SonicsGN™ v2.2 on-chip network IP improves support for memory subsystems and promotes performance with bandwidth allocation across multiple SoC flows. Incorporated memory subsystem and non-blocking concurrency technologies enable support for DDR4 and LPDDR4 memories for both compute and communication traffic on multi-core SoCs. Features fully support multi-threading capabilities of OCP interface, while scalable model ensures QoS allocates resource bandwidth and minimizes latencies. This story is related to the following:Electronic Components and DevicesSearch for suppliers of: Chip Networks
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