Reducing active and standby power consumption for mobile SoCs, Synopsys DesignWare® IP for PCIe® 3.1 specification helps designers extend mobile device battery life. L1 sub-states and power gating techniques, including utilization of power switches, power islands, or retention cells, reduce standby power to <10 µW/lane. Supply under drive, transmitter design, and equalization bypass schemes reduce active power to <5 mW/Gb/lane while meeting PCIe 3.1 electrical specification.