Intended for use-case, scenario-based software driven system-on-chip (SoC) verification, Cadence® Perspec™ System Verifier reduces complex test development to days while allowing design teams to reproduce, find, and fix complex bugs. Graphical specification of system-level verification scenarios and definition of SoC topology and actions automates system-level, coverage-driven test development using constraint solving technology. Tests run on all pre-silicon verification platforms.