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Synchronous SRAM promotes reliability via on-chip ECC.

2015-05-28 14:31:06| Industrial Newsroom - All News for Today

Supplied in RoHS-compliant, 100-pin TQFP and 165-ball BGA packages, 36 Mb synchronous SRAMs integrate on-chip Error-Correcting Code (ECC) that fosters data reliability while simplifying designs for military, communication, and data processing applications. All error correction functions are performed inline and without user intervention to deliver optimal Soft Error Rate performance. Operating over industrial temperature range, products are pin-compatible with current synchronous SRAMs.

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