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Synopsys Demonstrates Industry's First MIPI D-PHY IP Operating at 2.5 Gbps per Lane on TSMC 16-nm FinFET Plus Process

2015-10-26 11:31:11| Industrial Newsroom - All News for Today

Demonstration Validates Performance and Compliance of DesignWare MIPI D-PHY for Low-Risk Integration into Mobile SoCs MOUNTAIN VIEW, Calif. - Highlights:     --  Industry's first demonstration to be unveiled at the MIPI Alliance         Open and Demo Day in Taipei, October 29, 2015     --  Synopsys...

Tags: plus process operating lane

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