Featuring scalable multi-core architecture, 1.3 GHz CEVA-XC4500 DSP supports software-defined wireless infrastructure applications, targeting macrocells, small cells, cloud-RAN, digital front-end, and backhaul. Product incorporates baseband-dedicated ISA, IEEE-compliant floating point support on full vector elements delivering up to 40 GFLOPs performance, fully cached architecture, and hardware managed coherency. For LTE 2 x 2 Pico-Cell baseband processing, device requires as little as 100 mW.
This story is related to the following:Digital Signal Processors (DSP)