Designed to verify complex SoCs, Verification Compiler™ offers complete portfolio of integrated, next-generation verification technologies, including advanced debug capabilities built on Verdi 3™ debug platform, simulation, verification IP, and coverage closure. Static and formal verification technology supports formal property checking, low power static checking, and CDC checks as well as SoC connectivity checks, advanced lint and sequential equivalence checking.
This story is related to the following:Electronic Design Automation (EDA) Software | Simulation Software