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Tag: memory
ARM Cortex-M7 Based MCUs have configurable memory architecture.
2015-01-09 14:30:56| Industrial Newsroom - All News for Today
SMART™ ARM® Cortex®-M7 based MCUs contain memory architectures with up to 384 Kb multi-port SRAM, of which 256 Kb can be configured as tightly coupled memory delivering zero wait state access at 300 MHz. While SAM E70 and S70 suit connectivity and industrial applications, auto-grade SAM V70 and SAM V71 serve in-vehicle infotainment, audio amplifier, telematics, and head unit control applications. Features include USB OTG and on-chip USB PHY and 512 Kb, 1 MB, and 2 MB Flash memory densities.
Tags: based
memory
architecture
arm
Altera Demonstrates Industry's Highest Performance DDR4 Memory Data Rates in an FPGA
2014-12-29 11:32:29| Industrial Newsroom - All News for Today
2,666 Mbps DDR4 Memory Interface in Arria 10 FPGAs and SoCs Optimized for Data-Intensive Applications San Jose, Calif. Altera Corporation (Nasdaq: ALTR) today announced it is demonstrating in silicon DDR4 memory interfaces operating at an industry-leading 2,666 Mbps. Alteras Arria 10 FPGAs and SoCs are the...
Tags: data
performance
rates
highest
In Memory of Jack Hoogland
2014-12-25 03:29:48| Railroads - Topix.net
John William "Jack" Hoogland died peacefully at Providence Seward Medical Center on Saturday, December 20th, 2014, of complications from pneumonia. He had recently celebrated his 83rd birthday.
Researchers build room-temperature memory that doesnt need a current to retain data
2014-12-19 22:01:20| Extremetech
A new material from Cornell University researchers promises breakthroughs in device power consumption by dramatically cutting memory power. Will this achievement finally pan out?
Verification IP targets low-power memory controllers.
2014-12-17 14:31:30| Industrial Newsroom - All News for Today
Based on 100% native SystemVerilog Universal Verification Methodology architecture, Synopsys VIP for LPDDR4 comes with verification plans, built-in coverage, and protocol-aware memory debug environment. Transactor and monitor functions provide set of protocol, methodology, verification, and productivity features, enabling users to achieve rapid verification convergence on LPDDR4-based designs. VIP can also be dynamically configured to model any memory vendor component without need to recompile.
Tags: memory
targets
verification
controllers
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